16.04.2026

Operating Edge-Emitting Pulsed Laser Diodes with Short Pulses

Many existing and emerging applications for Edge-Emitting Pulsed Laser Diodes (hereafter referred to as simply PLDs) require operation of the devices with narrow pulse widths. These conditions may be necessary for ensuring eye-safe system certification or precision in distance measurement systems.

Short pulses also allow for reliable higher peak power operation of the devices. There are multiple challenges in generating short pulses with PLDs which will be discussed below.

PLDs - Electrical Characteristics

Basics

PLDs are current-controlled devices which emit radiation through the conversion of electrons into photons. Electrons provided by electrical current are injected into the device through conductors connected directly to the semiconductor. When enough electrons are applied in the forward bias direction, a lasing threshold is reached and the photons emitted are in direct and linear proportion to the electrons injected.

In the case of a PLD, the threshold can be ignored in system design since the operating point of the device is generally many times above threshold. The forward voltage drop across the device follows only a moderate slope versus the input current above threshold.

Modern quantum well PLDs convert electrons into optical power very efficiently typically 1 W/A for single junction emitters and 3.2 W/A for triple junction devices.

Circuit Design Considerations

Driving PLDs with Short Pulses

Figure 1

Switching the high current required for the PLDs is one of the main challenges in designing the drive electronics. Inductance in the circuit is a major obstacle in achieving short pulses. The basic formula

V = L (di/dt)

can be used to effectively predict the amount of voltage that will be required to achieve a desired current. As seen in the formula the current, time, and inductance (L) are all significant factors in determining the amount of voltage (V) necessary to deliver sufficient current to satisfy particular system requirements. For example, a 30 A pulse with a 1 ns rise time will correspond to a voltage drop of 30 V for each nH of inductance in the circuit.

Parasitic inductance is typically associated with the current carrying conductors in a circuit (loop). The longer these conductors are, the higher the inductance they impart on the loop and the more challenging the design becomes. The most effective means for managing inductance is to place the components in the loop as close as possible to one another. Figure 1 depicts a typical loop found in high peak current PLD driver designs. Where the capacitor (C) stores the energy for each pulse, transistor (Q) is a high speed switch, PLD is the edge emitting laser diode, HV is the charge voltage used to recharge (C) between pulses, the resistor (R) is used for current limiting on the recharge cycle and TRIG is the trigger signal used to turn on the switch. The value of (R) determines the pulse repetition frequency the circuit can deliver at full power.

Capacitor

critical for the performance of the PLD

Figure 2

Another important element to be considered when designing PLD drivers, which also contributes to the amount of voltage required to achieve a desired result, is the resistance of each component in the loop. These resistance values combine to effectively reduce the peak current flowing in the loop and will affect the temporal response of the circuit. Careful selection of components with the lowest possible series resistance is critical. This also holds true for the conductive materials used on PC boards or ceramic hybrid circuits.

The capacitor in the loop is critical for the performance of the PLD. When the transistor is switched on, the loop can be assumed to be a simple RC circuit. The time constant, which determines the pulse duration, can be calculated from τ = R_loopC . The loop current, provided by discharging the capacitor, can be estimated as

i = \frac{H V}{R_{l o o p}} e - \frac{t}{R_{l o o p} C}

A larger capacitor generates a wider and higher peak current pulse resulting in more powerful optical pulses.

Figure 2 shows the peak power versus HV for different capacitor values. The peak power at 80 V for instance is increased from 40 W to 100 W when the capacitance is increased from 330 pF to 2 nF.

Figure 3 and 4 present the pulse width and rise time versus HV for different capacitor values.
It is clear that a higher capacitance results in wider optical pulses.

Figure 3

Figure 4

The transistor which acts as a switch needs to hold-off high voltage in order to charge the capacitor. It is critical the transistor be selected to achieve the desired requirements from the PLD. The transistor needs to be small to reduce parasitic inductance.

Low series resistance and gate capacitance are also important to increase optical power and response time. Low series resistance will also help with thermal management. If a transistor can sustain high voltage and current, the capacitor can be charged with more electrons resulting in higher loop current.

Conclusion

It should be obvious now that in order to produce short current pulses to drive PLDs, either brute force or finessed circuit layout and careful component selection are required. Brute force of the HV is not always practical and can lead to undesirable pulse overshoot and ringing effects which can be detrimental to PLDs.